1. Field of the Invention
The present invention relates to a memory access circuit, and particularly to a memory access circuit that can be used for double data/single data rate applications.
2. Description of the Prior Art
Please refer to FIG. 1A, FIG. 1B and FIG. 1C. FIG. 1A is a diagram illustrating a memory access circuit 100 for double data rate application according to the prior art, FIG. 1B is a diagram illustrating the memory access circuit 100 writing double data rate data DDRD1, and a corresponding mask block signal MDDRD1, and FIG. 1C is a diagram illustrating the memory access circuit 100 reading double data rate data DDRD2. The memory access circuit 100 includes a write data circuit 102, a mask information circuit 104, a first odd term data input buffer 106, a first even term data input buffer 108, a read data circuit 120, a first odd term data output buffer 122, and a first even term data output buffer 124. As shown in FIG. 1B, after a first input buffer 1022 of the write data circuit 102 receives the double data rate data DDRD1, the first input buffer 1022 extracts odd term data DDRD1_O of the double data rate data DDRD1 to a second odd buffer 1024, and even term data DDRD1_E of the double data rate data DDRD1 to a second even buffer 1026, where a frequency of the odd term data DDRD1_O and a frequency of the even term data DDRD1_E is half of a frequency of the double data rate data DDRD1, and the odd term data DDRD1_O and the even term data DDRD1_E are related and parallel to each other. After a second input buffer 1042 of the mask information circuit 104 receives the mask block signal MDDRD1, the second input buffer 1042 extracts a mask block signal MDDRD1_O corresponding to the odd term data DDRD1_O of the double data rate data DDRD1 to a third odd buffer 1044, and a mask block signal MDDRD1_E corresponding to the even term data DDRD1_E of the double data rate data DDRD1 to a third even buffer 1046.
The first odd term data input buffer 106 receives the odd term data DDRD1_O and the mask block signal MDDRD1_O from the second odd buffer 1024 and the third odd buffer 1044, respectively, and transmits differential signals O1, O1B of odd term data DDRD1_O′ to two odd differential buses OB, OBB connected to an odd block of a memory according to the odd term data DDRD1_O and the mask block signal MDDRD1_O. The mask block signal MDDRD1_O is used for blocking partial odd term data of the odd term data DDRD1_O, and then the first odd term data input buffer 106 can generate the differential signals O1, O1B of the odd term data DDRD1_O′. The first even term data input buffer 108 receives the even term data DDRD1_E and the mask block signal MDDRD1_E from the second even buffer 1026 and the third even buffer 1046, respectively, and transmits differential signals E1, E1B of even term data DDRD1_E′ to two even differential buses EB, EBB connected to an even block of the memory according to the even term data DDRD1_E and the mask block signal MDDRD1_E. The mask block signal MDDRD1_E is used for blocking partial even term data of the even term data DDRD1_E, and then the first even term data input buffer 108 can generate the differential signals E1, E1B of the even term data DDRD1_E′.
As shown in FIG. 1C, an odd scheduling buffer 1202 of the read data circuit 120 receives odd term data DDRD2_O of double data rate data DDRD2 read and amplified by the first odd term data output buffer 122; an even scheduling buffer 1204 of the read data circuit 120 receives even term data DDRD2_E of the double data rate data DDRD2 read and amplified by the first even term data output buffer 124. An off-chip driver 1206 of the read data circuit 120 is used for increasing accuracy of the odd term data DDRD2_O and the even term data DDRD2_E, and outputting the double data rate data DDRD2.
Please refer to FIG. 2A, FIG. 2B, and FIG. 2C. FIG. 2A is a diagram illustrating a memory access circuit 200 for single data rate application according to the prior art, FIG. 2B is a diagram illustrating the memory access circuit 200 writing single data rate data SDRD1 and a mask block signal MSDRD1, and FIG. 2C is a diagram illustrating the memory access circuit 200 reading single data rate data SDRD2. The memory access circuit 200 includes a write data circuit 202, a mask information circuit 204, a first input register 206, a first output register 208, and a read data circuit 220. As shown in FIG. 2B, after a first input buffer 2022 of the write data circuit 202 receives the single data rate data SDRD1, the first input buffer 2022 stores the single data rate data SDRD1 to a second input register 2024. After a second input buffer 2042 of the mask information circuit 204 receives the mask block signal MSDRD1, the second input buffer 2042 stores the mask block signal MSDRD1 to a third input register 2044.
The first input register 206 receives the single data rate data SDRD1 and the mask block signal MSDRD1 from the second input register 2024 and the third input register 2044, respectively, and transmits differential signals S1, S1B of single data rate data SDRD1′ to two differential buses S, SB connected to a memory according to the single data rate data SDRD1 and the mask block signal MSDRD1. The mask block signal MSDRD1 is used for blocking partial data of the single data rate data SDRD1, and then the first input register 206 can generate the differential signals S1, S1B of the single data rate data SDRD1′. Therefore, the differential signals S1, S1B of the single data rate data SDRD1′ can be stored in the memory through the two differential buses S, SB.
As shown in FIG. 2C, a scheduling buffer 2202 of the read data circuit 220 receives single data rate data SDRD2′ read and amplified by the first output register 208. An off-chip driver 2206 of the read data circuit 220 is used for increasing accuracy of the single data rate data SDRD2′, and outputting the single data rate data SDRD2.
To sum up, in the prior art, the memory access circuit 100 and the memory access circuit 200 can not directly share the same memory. Therefore, the prior art may lose competitiveness as technology trends toward light and small memory chips.